EPM5130WC
| Parameters | |
|---|---|
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 100 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 100 |
| JESD-30 Code | R-CQFP-G100 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 64 |
| Clock Frequency | 33.3MHz |
| Propagation Delay | 55 ns |
| Organization | 19 DEDICATED INPUTS, 64 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 19 |
| In-System Programmable | NO |
| Height Seated (Max) | 2.99mm |
| Length | 19.2mm |
| Width | 14mm |
| RoHS Status | Non-RoHS Compliant |
| Surface Mount | YES |
EPM5130WC Overview
128macrocells exist, which are cells in a mobile phone network that are primarily composed of high-power towers, antennas, or masts.As a result, it has 64 I/O ports programmed.100terminations have been programmed into the device.Its terminal position is QUAD.Power is supplied by a voltage of 5V volts.The part belongs to Programmable Logic Devices family.A chip with 100pins is programmed.When using this device, LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCKis also available.Currently, it is powered by 5Vsources.There is a maximum supply voltage (Vsup) of 5.25V.The input signals are detected by 19dedicated inputs.It should be possible for Vsup to exceed 4.75Vat the supply voltage.This device should not have an clock frequency greater than 33.3MHz.This kind of FPGA is composed of UV PLD.It is recommended that the operating temperature remain below 70°C.
EPM5130WC Features
64 I/Os
100 pin count
5V power supplies
EPM5130WC Applications
There are a lot of Altera EPM5130WC CPLDs applications.
- Protection relays
- Timing control
- State machine design
- PLC analog input modules
- I/O expansion
- Voltage level translation
- I/O PORTS (MCU MODULE)
- Power Meter SMPS
- Storage Cards and Storage Racks
- Software-Driven Hardware Configuration