74ACT825SPC
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 24-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH TRIPLE OUTPUT ENABLE |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT APPLICABLE |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | NOT APPLICABLE |
| JESD-30 Code | R-PDIP-T24 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 158MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 80μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 9.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
74ACT825SPC Overview
The package is in the form of 24-DIP (0.300, 7.62mm). You can find it in the Tubepackage. The output it is configured with uses Tri-State, Non-Inverted. This trigger uses the value Positive Edge. Through Holeis occupied by this electronic component. The supply voltage is set to 4.5V~5.5V. A temperature of -40°C~85°C TAis used in the operation. The type of this D latch is D-Type. The 74ACTseries comprises this type of FPGA. In order for it to function properly, its output frequency should not exceed 158MHz. There are 1 elements in it. It consumes 80μA of quiescent current without being affected by external factors. There are 24 terminations,It is powered from a supply voltage of 5V. The input capacitance of this T flip flop is 4.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. The electronic device belongs to the ACTfamily. Vsup reaches 5.5V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be kept above 4.5V. There are 2 ports embedded in the flip flops. Additionally, it is characterized by WITH TRIPLE OUTPUT ENABLE.
74ACT825SPC Features
Tube package
74ACT series
74ACT825SPC Applications
There are a lot of Rochester Electronics, LLC 74ACT825SPC Flip Flops applications.
- Latch-up performance
- Memory
- EMI reduction circuitry
- Communications
- ESD performance
- ATE
- Bus hold
- Control circuits
- Single Down Count-Control Line
- Common Clocks